1. Field of the Invention
The present invention relates generally to a method of forming a gate in a semiconductor device, and more particularly, to a method of forming a metal gate in a semiconductor device using a damascene process.
2. Description of the Related Art
Semiconductor variables such, as gate width, gate insulating layer thickness, junction depth and the like are progressively being reduced as the integration of a semiconductor is increased. Fabrication methods of polysilicon gates fail to further realize the low resistance required for critical dimensions. In the mean time, developments for a gate having new gate material as a substitute for polysilicon and having new structure are necessitated. In the past, research and development efforts were focused on a polysilicide gate using transition metal-silicide materials.
Yet, the polysilicide gate still contains a polysilicon as a constituent, which results in increasing the difficulty in realizing low resistance. The polysilicon constituent in the polysilicide gate brings about increasingly effective thicknesses of a gate insulating layer due to a gate depletion effect, as well as threshold voltage variance due to boron penetration/dopant distribution fluctuation in a p+ doped polysilicon gate and the like, thereby limiting the ability to realize low resistance therein.
Boron penetration and gate depletion do not arise in a metal gate using no dopant. Moreover, metal gates use a metal having a work function value corresponding to a mid-band gap of silicon applied to a single gate, thereby enabling the formation of a symmetric threshold voltage in NMOS and PMOS areas. In this case, W, WN, Ti, TiN, Mo, Ta, TaN and the like comprise metals of which work function values correspond to the mid-gap of silicon.
If a semiconductor device is fabricated using a metal gate, difficulty arises in patterning a metal gate, i.e., difficulty of etching, plasma damages in the etching and ion implantation processes and thermal damage caused by a thermal process after the gate formation are generated, thereby reducing the device characteristics.
Accordingly, in order to overcome these perceived disadvantages, a method of forming a metal gate is proposed that includes the steps of forming a sacrificing gate of polysilicon, forming an insulating layer, removing the sacrificing gate, depositing a metal layer, and polishing the metal layer. The sacrificing gate is replaced by a metal gate, so that a gate is formed without using an etching process. Therefore, the damascene process avoids the problems caused by etching processes, and also enables use of the conventional semiconductor fabrication processes.
FIGS. 1A to 1G illustrate cross-sectional views of the steps of fabricating a MOSFET device having a tungsten gate using a conventional damascene process.
Referring to FIG. 1A, a field oxide layer, (not shown) defining a device active area, is formed on a surface of a semiconductor substrate land a dummy gate silicon oxide layer 2 is formed on the semiconductor substrate 1. A dummy gate polysilicon layer 3 and a hard mask layer 4 are then successively formed on the dummy gate silicon oxide layer 2.
Referring to FIG. 1B, a mask pattern 4a is formed by patterning the hard mask layer 4. A dummy gate 5 is then formed by etching the dummy gate polysilicon layer 3 and silicon oxide layer 2 using the mask pattern 4a. 
Referring to FIG. 1C, LDD (lightly doped drain) regions are formed in portions of the silicon substrate 1 below both lateral sides of the dummy gate 5 by ion implantation at a relatively low dose and energy. Then, spacers 6 are formed at both sidewalls of the dummy gate 5 by using known processes. Subsequently, source region s and drain region d are formed at the portions of the semiconductor substrate 1 below both lateral sides of the dummy gate 5 by heavy ion implantation.
Referring to FIG. 1D, an insulating interlayer 7 is deposited on the semiconductor substrate 1. The dummy gate polysilicon layer 3 of the dummy gate 5 is exposed by planarizing a surface of the insulating interlayer 7 by using chemical mechanical polishing (hereinafter abbreviated CMP) on the insulating interlayer 7.
Referring to FIG. 1D, the dummy gate, exposed by CMP, is removed. Now referring to FIG. 1E, a gate insulating layer 8 is then formed along a surface of the resultant structure. Subsequently, a gate metal layer 9, such as a tungsten layer, is deposited on the gate insulating layer 8.
Referring to FIG. 1F, a metal gate is formed by polishing the gate metal layer 9 and the gate insulating layer 8 until the insulating interlayer 7 is exposed. Thus, a MOSFET device having the metal gate is completed, as shown.
Unfortunately, the gate formed by using the conventional damascene process has disadvantages, as described below.
In a semiconductor fabrication process, a device isolation process has to precede the gate electrode formation and a gate electrode line traverses active and field areas simultaneously. As shown in FIG. 2, the surface of a field oxide layer 11 is generally higher than the surface of the semiconductor substrate 1 in the active area t in the device isolation process. Thus, a step difference a shown in FIG. 2 as the gap between the top portion of the field oxide layer 11 defining the field area h (FIG. 2) and the top portion of the semiconductor substrate, a mid-portion of which is defined as the active area t is generally between 200 to 500 Å.
A general CMP process completely planarizes an entire surface regardless of the field and active areas h and t along a dotted line AA′. This causes a problem in forming a poly wordline having an irregular thickness if the polishing process is carried out until the dummy gate polysilicon layer 3 is exposed, as shown in FIG. 1D. Yet, a surface of the polysilicon layer 3 has to be exposed by the CMP process in order to form the gate electrode using the conventional damascene process. Considering the height of the field oxide layer, the deposited thickness of the polysilicon layer 3 needs to be higher by at least an additional height a to make up for the step difference. Therefore, the hard mask layer for patterning the polysilicon layer has to be thicker by about 100 Å.
Consequently, the total height of the dummy gate 5 becomes taller by 300 to 600 Å, whereby the steps of etching the dummy gate polysilicon layer, removing the dummy gate selectively, and filling the gate metal layer into the space where the dummy gate is removed become difficult to carry out.